General Description

The CS5510/11/12/13 are low-cost, easy-to-use, ?Σ analog-to-digital converters (ADCs) which use chargebalance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) performance. The ADCs are available in a space-efficient, 8-pin SOIC package and are optimized for measuring signals in weigh scale, process control, and other industrial applications.

Features

● Delta-sigma Analog-to-digital Converter

– Linearity Error: 0.0015 FS

– Noise-free Resolution: Up to 17 Bits

● Differential Bipolar Analog Inputs

● VREF Input Range from 250 mV to 5 V

● 50/60 Hz Simultaneous Rejection (CS5510/12)

● 16 to 326 Sps Output Word Rate

● On-chip Oscillator (CS5511/13)

● Power Supply Configurations:

– V+ = 5 V, V- = 0 V

– Multiple Dual-supply Arrangements

● zLow Power Consumption

– Normal Mode, 2.5 mW

– Sleep Mode, 10 μW

● Low-cost, Compact, 8-pin Package

● Lead-free Device Package Options

CS5510-AS屬于集成電路（IC） > 模數(shù)轉(zhuǎn)換器（ADC）。凌云邏輯制造生產(chǎn)的CS5510-AS模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。