General Description

The CS42416 codec provides two analog-to-digital and six digital-to-analog delta-sigma converters, as well as an integrated PLL.

The CS42416 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All six channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.

Features

? Six 24-bit D/A, two 24-bit A/D Converters

? 110 dB DAC / 114 dB ADC Dynamic Range

? -100 dB THD+N

? System Sampling Rates up to 192 kHz

? Integrated Low-Jitter PLL for Increased System Jitter Tolerance

? PLL Clock or System Clock Selection

? 7 Configurable General-Purpose Outputs

? ADC High-Pass Filter for DC Offset Calibration

? Expandable ADC Channels and One-Line Mode Support

? Digital Output Volume Control with Soft Ramp

? Digital +/-15 dB Input Gain Adjust for ADC

? Differential Analog Architecture

? Supports Logic Levels between 1.8 V and 5 V

CS42416屬于集成電路（IC） > 編解碼器。凌云邏輯制造生產(chǎn)的CS42416編解碼器編解碼器是用于通過(guò)壓縮和解壓縮來(lái)轉(zhuǎn)換數(shù)據(jù)的半導(dǎo)體器件。數(shù)據(jù)壓縮可提高傳輸速度并減少存儲(chǔ)空間。某些編解碼器提供高達(dá) 32 位的分辨率，并且分別提供多達(dá) 6 個(gè)或 8 個(gè)模數(shù)轉(zhuǎn)換器和數(shù)模轉(zhuǎn)換器。除三角積分調(diào)制外，還有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 數(shù)據(jù)接口。