CD4541BF中文資料HARRIS數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the MASTER RESET input.

Features

? Low Symmetrical Output Resistance, Typically 100? at VDD = 15V

? Built-In Low-Power RC Oscillator

? Oscillator Frequency Range . . . . . . . . . . DC to 100kHz

? External Clock (Applied to Pin 3) can be Used Instead of Oscillator

? Operates as 2N Frequency Divider or as a Single Transition Timer

? Q/Q Select Provides Output Logic Level Flexibility

? AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation

? Operates With Very Slow Clock Rise and Fall Times

? Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range

? Symmetrical Output Characteristics

? 100 Tested for Quiescent Current at 20V

? 5V, 10V, and 15V Parametric Ratings

? Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”