AT40KFL040中文資料愛特梅爾數(shù)據(jù)手冊PDF規(guī)格書

Description

The AT40KEL040 is a fully PCI-compliant, SRAM-based FPGA with distributed 18 ns programmable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and 46,000 ASIC gates. I/O counts range from 129 to 384 in Aerospace standard packages and support 3.3V.

Features

? SRAM based FPGA Dedicated to Space Use

? SEE Hardened Cells (configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) Remove the need for Triple Modular Redundancy (TMR)

? Produced on Rad Hard 0.35μm CMOS Process

? Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series

? High Performance

– 46K Available ASIC gates (50 typ. routable)

– 60 MHz Internal Performance

– 20 MHz System Performance

– 30 MHz Array Multipliers

– 18 ns FreeRAM? access time

– Internal Tri-state Capability in Each Cell

? FreeRAM

– 18432 Bits of Distributed SRAM Independent of Logic Cells

– Flexible, Single/Dual Port, Synchronous/Asynchronous 32x4 RAM blocks

? 8 Global Clocks and 4 Additional Dedicated PCI Clocks

– Fast, Low Skew Clock Distribution

– Programmable Rising/Falling Edge Transitions

– Distributed Clock Shutdown Capability for Low Power Management

? Global Reset Option

? 384 PCI Compliant I/Os

– Programmable Output Drive

– Fast, Flexible Array Access Facilitates Pin Locking

? Package Options

– MQFPF160

– MQFPF256

? Design Software (System Designer)

– Combination of Atmel internally developed tools, and industry standard design tools

– Fast and Efficient Synthesis

– Efficient Integration (Libraries, Interface, Full Back-annotation)

– Over 75 Automatic Component Generators Create Thousands of Speed and Area Optimized Logic and RAM Functions

– Automatic/Interactive Multi-chip Partitioning

? Supply Voltage 3.3V

? AT40KFL040 is a 5V Tolerant Version

? No Single Event Latch-up below a LET Threshold of 70 MeV/mg/cm2

? Tested up to a Total Dose of 300 krads (Si) according to MIL STD 883 Method 1019

? Quality Grades

– QML -Q and -V with SMD 5962-03250

– ESCC with 9304/008

? Design Kit (AT40KEL-DK) Including:

– A Board with the RH FPGA (MQFPF160 or MQFPF256)

– A configuration memory (AT17 Atmel EEPROM)

– Design software and documentation

– ISP cable and software

? Easy Migration to Atmel Gate Arrays for High Volume Production