AS1160-BCTT中文資料艾邁斯歐司朗數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General Description

The AS1160 (serializer) is designed to convert 10-bit wide parallel LVCMOS/LVTTL data bus signals into a single high-speed LVDS serial data stream with clock. The AS1161 (deserializer) transforms the high-speed LVDS serial data stream back into a 10-bit wide parallel data bus with recovered parallel clock.

Key Features

■ Serial Bus LVDS Data Rate: 660 Mbps @ 66MHz Clock

■ 10-bit Parallel Interface

■ Synchronization Mode and Lock Indicator

■ Programmable Edge Trigger on Clock

■ High Impedance on Rx Inputs during Poweroff

■ Bus LVDS Serial Output Load: 28Ω

■ IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode

■ Clock Recovery from PLL Lock to Random Data Patterns

■ Guaranteed Transition each Data Transfer Cycle

■ Chipset (Tx + Rx) Power Consumption: < 500 mW @ 66MHz

■ Single Differential-Pair eliminates Multi-Channel Skew

■ Flow-Through Pinout for Simple PCB Layout

■ Small CTBGA 49-bumps Package

Applications

The devices are ideal for cellular phone base stations, add drop muxes, digital cross-connects. DSLAMs, networkswitches and routers or backplane interconnect.