AM8251中文資料ETC數(shù)據手冊PDF規(guī)格書

DISTINCTIVE CHARACTERISTICS

? Improved performance with Am9551

? Separate control and transmit register input buffers

? 8080A/9080A compatible

? Synchronous or asynchronous serial data transfer

? Parity, overrun and framing errors detected

? Half or full duplex signalling

? Character length of 5, 6, 7 or 8 bits

? Internal or external synchronization

? Odd parity, even parity or no parity bit

? Modem interface controlled by processor

? Programmable Sync pattern

? Fully TTL compatible logic levels

? +5 only power supply

? Commercial and military temperature range operation

? Ion-implanted N-channel silicon gate MOS technology

? 100 M I L-STD-883 reliabi lity assurance testing

GENERAL DESCRIPTION

The Am8251/9551 is a programmable serial data communication interface that provides a Universal Synchronous/Asynchronous Receiver/Transmitter (USART) function_ It is normally used as a peripheral device for an associated processor,

and may be programmed by the processor to operate in a

variety of standard serial communication formats.

The device accepts parallel data from the CPU, formats and

serializes the information based on its current operating mode,

and then transmits the data as a serial bit stream. Simultaneously, serial data can be received, converted into parallel form,

de-formated, and then presented to the CPU. The USART can

operate in an independent full duplex mode.

Data, Control, operation and format options are all selected by

commands from an associated processor. This provides an

unusual degree of flexibility and allows the Am8251/9551 to

service a wide range of communication disciplines and applications.

INTERFACE SIGNAL DESCRIPTION

Data Bus

The Am9551 uses an 8 bit bi-directional data bus to exchange

information with an associated processor. Internally, data is

routed between the data bus buffers and the transmitter section or receiver section as selected by the Read (RD) or Write

(WR) control inputs.

Chip Select (CS)

The active low Chip Select input allows the Am9551 to be individually selected from other devices within its address range.

When Chip Select is high, reading or writing is inhibited, and

the data bus output is in it's high impedance state.

Reset

The Am9551 will assume an idle state when a high level is

applied to the Reset input. When the Reset is returned low,

the Am9551 will remain in the idle state until it receives a new

mode control instruction.

Read (RD)

The active low Read input enables data to be transferred from

the Am9551 to the processor.

Write (WR)

The active low Write input enables data to be transferred from

the processor to the Am9551.

Control/Data (C/O)

During a Read operation, if this input is at a high level the

status byte will be read, and if it is at a low level the receive

data will be read by the processor. When a Write operation is

being performed, this input will indicate to the Am9551 that

the bus information being written is a command if ci5 is high

and data if cio is low.

Clock (ClK)

This input is used for internal timing within the Am9551. It

does not control the transmit or receive rate. However, it

should be at least 30 times the receive or transmit rate in the

synchronous mode and 4.5 times the receive or transmit rate

in the asynchronous mode. The ClK frequency is also restricted by both an upper and a lower bound. This input is

often connected to a clock from the associated processor.

Receiver Data (RxD)

Serial data is received from the communication line on this

input.

Receiver Clock (RxC)

The serial data on input RxD is clocked into the Am9551 by

the RxC clock signal. In the synchronous mode, RxC is determined by the baud rate and supplied by the modem. In the

asynchronous mode, RxC is 1, 16, or 64 times the baud rate as

selected in the mode control instruction. Data is sampled by

the Am9551 on the rising edge of RxC.

Receiver Ready (RxRDY)

The RxRDY output signal indicates to the processor that data

has been shifted into the receiver buffer from the receiver section and may be read. The signal is active high and will be re7-37

Am8251 ? Am9551

set when the buffer is read by the processor. RxRDY can be

activated only if the receiver enable (RxE) has been set in the

command register, even though the receiver may be running.

If the processor does not read the receiver buffer before the

next character is shifted from the receiver section then an

overrun error will be indicated in the status buffer.

Sync Detect (SYNDET)

This signal is used only in the synchronous mode. It can be

either an output or input depending on whether the program

is set for internal or external synchronization. As an output,

a high level indicates when the sync character has been detected in the received data stream after the Internal Synchronization mode has been programmed. If the Am9551 is programmed to utilize two sync characters, then SYNDET will go

to a high level when the last bit of the second sync character

is received. SYNDET is reset when the status buffer is read or

when a Reset signal is activated. SYNDET will perform as an

input when the External Synchronization mode is programmed.

External logic can supply a positive-going signal to indicate to

the Am9551 that synchronization has been attained. This will

cause it to initialize the assembly of characters on the next

falling edge of RxC. To successfully achieve synchronization

the SYNDET signal should be maintained in a high condition

for at least one full period of RxC.

Transmit Data (TxD)

Serial data is transmitted to the communication line on this

output.

Transmitter Clock (TxC)

The serial data on TxD is clocked out with the TxC signal. The

relationship between clock rate and baud rate is similar to that

for RxC. Data is shifted out of the Am9551 on the falling edge

of TxC.

Transmitter Ready (TxRDY)

The TxRDY output signal goes high when data in the Transmit

Data Buffer has been shifted into the transmitter section allowing the Transmit Data Buffer to accept the next byte from

the processor. TxRDY will be reset when information is written into the Transmit Data Buffer. loading command register

also resets TxRDY. TxRDY will be available on this output

pin only when the Am9551 is enable to transmit (CTS = 0,

TxEN = 1). However, the TxRDY bit in the status Buffer will

always be set when the Transmit Data Buffer is empty regardless of the state of TxEN and CTS.

Transmitter Empty (TxE)

The TxE output signal goes high when the Transmitter section

has transmitted its data and is empty. The signal will remain

high until a new data byte is shifted from the Transmit Data

Buffer to the Transmitter section. In the synchronous mode if

the processor does not load a new byte into the buffer in time,

TxE will, independent of the status of the TxEN bit in the

command register, momentarily go to a high level as SYNC

characters are loaded into the Transmitter Section.

Data Terminal Ready (DTR)

This signal is a general purpose output which reflects the state

of bit 1 in the Command instruction. It is commonly connected

to an associated modem to indicate that the Am9551 is ready.

Data Set Ready (DSR)

This is a general purpose input signal and forms part of the status byte that may be read by the processor. DSR is generally

used as a response to DTR, by the Modem, to indicate that it

is ready. The signal acts only as a flag and does not control

any internal logic.