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AM79C940VCW規(guī)格書詳情
GENERAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specifically designed to address applications where multiple I/O peripherals are present, and a centralized or system specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an external DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers.
The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architecture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system.
DISTINCTIVE CHARACTERISTICS
■ Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port
■ Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards
■ 84-pin PLCC and 100-pin PQFP Packages
■ 80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA
■ Modular architecture allows easy tuning to specific applications
■ High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer
■ Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of collision frames
— Automatic retransmission with no FIFO reload
■ Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs
■ Direct FIFO read/write access for simple interface to DMA controllers or l/O processors
■ Arbitrary byte alignment and little/big endian memory interface supported
■ Internal/external loopback capabilities
■ External Address Detection Interface (EADI?) for external hardware address filtering in bridge/router applications
■ JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test
■ Integrated Manchester Encoder/Decoder
■ Digital Attachment Interface (DAI?) allows by-passing of differential Attachment Unit Interface (AUI)
■ Supports the following types of network interface:
— AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU
— DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU
— General Purpose Serial Interface (GPSI) to external encoding/decoding scheme
— Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port
■ Sleep mode allows reduced power consumption for critical battery powered applications
■ 5 MHz-25 MHz system clock speed
■ Support for operation in industrial temperature range (–40°C to +85°C) available in all three packages
產品屬性
- 型號:
AM79C940VCW
- 制造商:
AMD
- 制造商全稱:
Advanced Micro Devices
- 功能描述:
Media Access Controller for Ethernet(MACE)
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
AMD |
23+ |
NA/ |
13 |
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價 | ||
AMD |
22+ |
TQFP80 |
12245 |
現(xiàn)貨,原廠原裝假一罰十! |
詢價 | ||
AMD |
23+ |
QFP |
8650 |
受權代理!全新原裝現(xiàn)貨特價熱賣! |
詢價 | ||
AMD |
24+ |
QFP |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
AMD |
23+ |
QFP |
5000 |
原廠授權代理,海外優(yōu)勢訂貨渠道??商峁┐罅繋齑?詳 |
詢價 | ||
AMD |
04+ |
QFP |
300 |
詢價 | |||
AMD |
22+ |
QFP |
2258 |
大量現(xiàn)貨庫存,提供一站式服務! |
詢價 | ||
23+ |
QFP |
7300 |
專注配單,只做原裝進口現(xiàn)貨 |
詢價 | |||
AMD |
23+ |
QFP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價 | ||
AMD |
23+ |
QFP-160P |
7750 |
全新原裝優(yōu)勢 |
詢價 |