AM68AX中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

1 Features

Processor cores:

? Up to dual 64-bit Arm? Cortex?-A72

microprocessor subsystem at up to 2 GHz

– 1MB shared L2 cache per dual-core Cortex?-

A72 cluster

– 32KB L1 D-Cache and 48KB L1 I-Cache per

Cortex?-A72 core

? Deep Learning Accelerator:

– Up to 8 Trillion Operations Per Second (TOPS)

? Vision Processing Accelerators (VPAC) with Image

Signal Processor (ISP) and multiple vision assist

accelerators

? Dual-core Arm? Cortex?-R5F MCUs at up to 1.0

GHz in General Compute partition with FFI

– 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB

L2 TCM

? Dual-core Arm? Cortex?-R5F MCUs at up to 1.0

GHz to support Device Management

– 32K L1 D-Cache, 32K I-Cache, and 64K L2

TCM with SECDED ECC on all memories

? Vision Processing Accelerators (VPAC) with Image

Signal Processor (ISP) and multiple vision assist

accelerators

– 480 MPixel/s ISP

– Support for up to 16-bit input RAW format

– Wide Dynamic Range (WDR), Lens Distortion

Correction (LDC), Vision Imaging Subsystem

(VISS), and Multi-Scalar (MSC) support

– Output color format : 8-bits, 12-bits, and YUV

4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

? Display subsystem supports:

– Up to 4 displays

– Up to two DSI 4L TX (up to 2.5K)

– One eDP 4L

– One DPI 24-bit RGB parallel interface

– OLDI/LVDS (4 lanes - 2x) and 24-bit RGB

parallel interface

– Safety features such as freeze frame detection

and MISR data check

? 3D Graphics Processing Unit

– IMG BSX-64-4, up to 800 MHz

– 50 GFLOPS, 4 GTexels/s

– >500 MTexels/s, >8 GFLOPs

– Supports at least 2 composition layers

– Supports up to 2048x1080 @60fps

– Supports ARGB32, RGB565 and YUV formats

– 2D graphics capable

– OpenGL ES 3.1, Vulkan 1.2

? Two CSI2.0 4L Camera Serial interface (CSI-Rx)

Plus CSI2.- 4L Tx (CSI-Tx) with DPHY

– MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2

– Support for 1,2,3, or 4 data lane mode up to

1.5Gbps

– ECC verification/correction with CRC check +

ECC on RAM

– Virtual Channel support (up to 16)

– Ability to write stream data directly to DDR via

DMA

? Video Encoder/Decoder

– Support for HEVC (H.265) Main profiles at

Level 5.1 High-tier

– Support for H.264 BaseLine/Main/High Profiles

at Level 5.2

– Support for up to 4K UHD resolution (3840 ×

2160)

– 4K60 H.264/H.265 Encode/Decode (up to 480

MP/s)

Memory subsystem:

? Up to 4MB of on-chip L3 RAM with ECC and

coherency

– ECC error protection

– Shared coherent cache

– Supports internal DMA engine

? Up to two External Memory Interface (EMIF)

modules with ECC

– Supports LPDDR4 memory types

– Supports speeds up to 4266 MT/s

– Up to two 32-bit data bus with inline ECC up to

17 GB/s per EMIF

? General-Purpose Memory Controller (GPMC)

? Up to two 512KB on-chip SRAM in MAIN domain,

protected by ECC

Device security:

? Secure boot with secure run-time support

? Customer programmable root key, up to RSA-4K

or ECC-512

? Embedded hardware security module

? Crypto hardware accelerators – PKA with ECC,

AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

? One PCI-Express? (PCIe) Gen3 controllers

– Up to four lanes per controller

– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3

(8.0GT/s) operation with auto-negotiation

? One USB 3.0 dual-role device (DRD) subsystem

– Enhanced SuperSpeed Gen1 Port

– Supports Type-C switching

– Independently configurable as USB host, USB

peripheral, or USB DRD

? Two CSI2.0 4L RX plus Two CSI2.04L TX

? Two Ethernet RMII/RGMII interfaces

Flash memory interfaces:

? Embedded MultiMediaCard Interface (eMMC? 5.1)

? One Secure Digital? 3.0/Secure Digital Input

Output 3.0 interfaces (SD3.0/SDIO3.0)

? Two simultaneous flash interfaces configured as

– One OSPI or HyperBus? or QSPI, and

– One QSPI

Technology / Package:

? 16-nm FinFET technology

? 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA

(ALZ)

2 Applications

? Machine Vision Camera and computers

? Smart shopping cart

? Retail automation

? Smart agriculture

? Video surveillance

? Traffic monitoring

? Autonomous Mobile Robots (AMR)

? Drone

? Industrial transport

? Industrial Human Machine Interfaces (HMI)

? Industrial PC

? Single board computers

? Patient monitoring and medical devices

3 Description

The AM68A scalable processor family is based on the evolutionary Jacinto? 7 architecture, targeted at Smart

Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s

leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive highperformance

compute applications in Factory Automation, Building Automation, and other markets.

The AM68A provides high performance compute technology for both traditional and deep learning algorithms

at industry leading power/performance ratios with a high level of system integration to enable scalability and

lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for

general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional

algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU

island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm?

Cortex?-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm?

Cortex?-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm? Cortex?-A72

core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes

flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics

applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the

integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000? DSP next generation core (“C7x”) combines TI’s industry

leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation

capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new

“MMA” deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within

the lowest power envelope in the industry even when operating even at the worst case junction temperatures of

105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on

system performance. The C7x/MMA cores are available only for deep learning function in the AM68A class of

processors.