1 Features

Processor Cores:

? Up to Quad 64-bit Arm? Cortex?-A53

microprocessor subsystem at up to 1.4 GHz

– Quad-core Cortex-A53 cluster with 512KB L2

shared cache with SECDED ECC

– Each A53 Core has 32KB L1 DCache with

SECDED ECC and 32KB L1 ICache with

Parity protection

? Single-core Arm? Cortex?-M4F MCU at up to

400 MHz

– 256KB SRAM with SECDED ECC

? Dedicated Device/Power Manager

Multimedia:

? Display subsystem

– Dual display support

– 1920x1080 @ 60fps for each display

– 1x 2048x1080 + 1x 1280x720

– Up to 165 MHz pixel clock support with

Independent PLL for each display

– OLDI (4 lanes LVDS - 2x) and

DPI (24-bit RGB LVCMOS)

– Support safety feature such as freeze frame

detection and MISR data check

? 3D Graphics Processing Unit

– 1 pixel per clock or higher

– Fillrate greater than 500 Mpixels/sec

– >500 MTexels/s, >8 GFLOPs

– Supports at least 2 composition layers

– Supports up to 2048x1080 @60fps

– Supports ARGB32, RGB565 and YUV formats

– 2D graphics capable

– OpenGL ES 3.1, Vulkan 1.2

? One Camera Serial interface (CSI-Rx) - 4 Lane

with DPHY

– MIPI? CSI-2 v1.3 Compliant + MIPI D-PHY 1.2

– Support for 1,2,3 or 4 data lane mode up to

1.5Gbps per lane

– ECC verification/correction with CRC check +

ECC on RAM

– Virtual Channel support (up to 16)

– Ability to write stream data directly to DDR via

DMA

Memory Subsystem:

? Up to 816KB of On-chip RAM

– 64KB of On-chip RAM (OCSRAM) with

SECDED ECC , Can be divided into smaller

banks in increments of 32KB for as many as 2

separate memory banks

– 256KB of On-chip RAM with SECDED ECC in

SMS Subsystem

– 176KB of On-chip RAM with SECDED ECC in

SMS Subsystem for TI security firmware

– 256KB of On-chip RAM with SECDED ECC in

Cortex-M4F MCU subsystem

– 64KB of On-chip RAM with SECDED ECC in

Device/Power Manager Subsystem

? DDR Subsystem (DDRSS)

– Integrated 512MB LPDDR4 SDRAM

– Supports speeds up to 1600 MT/s

– 16-Bit data bus with inline ECC

Security:

? Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

? Trusted Execution Environment (TEE) supported

– Arm TrustZone? based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

– Secure storage support

– Replay Protected Memory Block (RPMB)

support

? Dedicated Security Controller with user

programmable HSM core and dedicated security

DMA & IPC subsystem for isolated processing

? Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

? Supports cryptographic cores

– AES – 128-/192-/256-Bit key sizes

– SHA2 – 224-/256-/384-/512-Bit key sizes

– DRBG with true random number generator

– PKA (Public Key Accelerator) to Assist in

RSA/ECC processing for secure boot

? Debugging security

– Secure software controlled debug access

– Security aware debugging

PRU Subsystem:

? Dual-core Programmable Real-Time Unit

Subystem (PRUSS) running up to 333 MHz

? Intended for driving GPIO for cycle accurate

protocols such as additional:

– General Purpose Input/Output (GPIO)

– UARTs

– I2C

– External ADC

? 16KByte program memory per PRU with

SECDED ECC

? 8KB data memory per PRU with SECDED ECC

? 32KB general purpose memory with

SECDED ECC

? CRC32/16 HW accelerator

? Scratch PAD memory with 3 banks of

30 x 32-bit registers

? 1 Industrial 64-bit timer with 9 capture and

16 compare events, along with slow and fast

compensation

? 1 interrupt controller (INTC), minimum of 64 input

events supported

High-Speed Interfaces:

? Integrated Ethernet switch supporting

(total of 2 external ports)

– RMII(10/100) or RGMII (10/100/1000)

– IEEE1588 (Annex D, Annex E, Annex F with

802.1AS PTP)

– Clause 45 MDIO PHY management

– Packet Classifier based on ALE engine with

512 classifiers

– Priority based flow control

– Time sensitive networking (TSN) support

– Four CPU H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

? Two USB2.0 Ports

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device (DRD mode)

– Integrated USB VBUS detection

General Connectivity:

? 9x Universal Asynchronous Receiver-Transmitters

(UART)

? 5x Serial Peripheral Interface (SPI) controllers

? 6x Inter-Integrated Circuit (I2C) ports

? 3x Multichannel Audio Serial Ports (McASP)

– Transmit and Receive Clocks up to 50 MHz

– Up to 16/10/6 Serial Data Pins across 3x

McASP with Independent TX and RX Clocks

– Supports Time Division Multiplexing (TDM),

Inter-IC Sound (I2S), and Similar Formats

– Supports Digital Audio Interface Transmission

(SPDIF, IEC60958-1, and AES-3 Formats)

– FIFO Buffers for Transmit and Receive

(256 Bytes)

– Support for audio reference output clock

? 3x enhanced PWM modules (ePWM)

? 3x enhanced Quadrature Encoder Pulse modules

(eQEP)

? 3x enhanced Capture modules (eCAP)

? General-Purpose I/O (GPIO), All LVCMOS I/O can

be configured as GPIO

? 3x Controller Area Network (CAN) modules with

CAN-FD support

– Conforms w/ CAN Protocol 2.0 A, B and ISO

11898-1

– Full CAN FD support (up to 64 data bytes)

– Parity/ECC check for Message RAM

– Speed up to 8Mbps

Media and Data Storage:

? 3x Multi-Media Card/Secure Digital?

(MMC/SD?/SDIO) interface

– 1x 8-bit eMMC interface up to HS200 speed

– 2x 4-bit SD/SDIO interface up to UHS-I

– Compliant with eMMC 5.1, SD 3.0 and

SDIO Version 3.0

? 1× General-Purpose Memory Controller (GPMC)

up to 133 MHz

– Flexible 8- and 16-Bit Asynchronous Memory

Interface With up to four Chip (22-bit address)

Selects (NAND, NOR, Muxed-NOR, and

SRAM)

– Uses BCH Code to Support 4-, 8-, or 16-Bit

ECC

– Uses Hamming Code to Support 1-Bit ECC

– Error Locator Module (ELM)

? Used With the GPMC to Locate Addresses

of Data Errors From Syndrome Polynomials

Generated Using a BCH Algorithm

? Supports 4-, 8-, and 16-Bit Per 512-Byte

Block Error Location Based on BCH

Algorithms

? OSPI/QSPI with DDR / SDR support

– Support for Serial NAND and Serial NOR flash

devices

– 4GBytes memory address support

– XIP mode with optional on-the-fly encryption

Power Management:

? Low power modes supported by Device/Power

Manager

– Partial IO support for CAN/GPIO/UART wakeup

– DeepSleep

– MCU Only

– Standby

– Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

? Recommended TPS65219 Power Management

ICs (PMIC)

– Companion PMIC specially designed to meet

device power supply requirements

– Flexible mapping and factory programmed

configurations to support different use cases

Boot Options:

? UART

? I2C EEPROM

? OSPI/QSPI Flash

? GPMC NOR/NAND Flash

? Serial NAND Flash

? SD Card

? eMMC

? USB (host) boot from Mass Storage device

? USB (device) boot from external host (DFU mode)

? Ethernet

Technology / Package:

? 16-nm technology

? 13 mm x 13 mm, 0.5-mm pitch, 425-pin

FCCSP BGA (AMK)

2 Applications

? Human Machine Interfaces (HMI)

? Medical equipment, Patient monitoring, and Portable medical devices

? Appliance user interface and connectivity

? Electric Vehicle Service Equipment (EVSE) / Vehicle to Infrastructure (V2X)

? Smart home gateways

? Embedded security: Control & Access panels

3 Description

AM625SIP is a System In Package (SIP) derivative of the ALW packaged AM6254 device, with the addition of

an integrated LPDDR4 SDRAM. This document only defines differences or exceptions to the ALW packaged

AM6254 device defined in AM62x Sitara Processors Datasheet (revision B or later).

The AM625SIP (System in Package) Sitara? MPU with integrated LPDDR4 is an application processor built

for Linux development. The system in package integrates 512MB of LPDDR4 with the AM6254 device which

has 4x Arm? Cortex?-A53 performance and embedded features, such as: dual-display support, 3D graphics

acceleration, along with an extensive set of peripherals that make the System in package well-suited for a broad

range of industrial applications while offering intelligent features and optimized power architecture. Additionally,

the AM625SIP offers a simplified hardware design, increased robustness, optimized size/system BOM, and

power consumption savings all enabling faster software and hardware development.

Some of these applications include:

? Industrial HMI

? Medical equipment, Patient monitoring, and Portable medical devices

? Smart home gateways & Appliances

? Embedded security: Control & Access panels

The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking

(TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own

use cases. In addition, the extensive set of peripherals included in AM625SIP enables system-level connectivity,

such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external

ASIC/FPGA. The AM625SIP device also supports secure boot for IP protection with the built-in Hardware

Security Module (HSM) and employs advanced power management support for portable and power-sensitive

applications