ADSP-BF537BBC-5A集成電路（IC）的DSP（數(shù)字信號(hào)處理器）規(guī)格書PDF中文資料

ADSP-BF537BBC-5A屬于集成電路（IC）的DSP（數(shù)字信號(hào)處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADSP-BF537BBC-5ADSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。

GENERAL DESCRIPTION

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISClike microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter

RISC-like register and instruction model for ease of programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core VDD with on-chip voltage regulation

2.5 V and 3.3 V-tolerant I/O with specific 5 V-tolerant pins

182-ball and 208-ball MBGA packages

MEMORY

Up to 132K bytes of on-chip memory comprised of:

Instruction SRAM/cache; instruction SRAM; data SRAM/cache; additional dedicated data SRAM; scratchpad SRAM (see Table 1 on Page 3 for available memory configurations)

External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI and TWI memory or from SPI, TWI, and UART host devices

Memory management unit providing memory protection

PERIPHERALS

IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and ADSP-BF537 only)

Controller area network (CAN) 2.0B interface

Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats

Two dual-channel, full-duplex synchronous serial ports (SPORTs), supporting eight stereo I2S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

Two memory-to-memory DMAs with external request lines

Event handler with 32 interrupt inputs

Serial peripheral interface (SPI)-compatible

Two UARTs with IrDA? support

Two-wire interface (TWI) controller

Eight 32-bit timer/counters with PWM support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), 8 with high current drivers

On-chip PLL capable of 1 x to 63 x frequency multiplication

Debug/JTAG interface