ADSP-21061KS-133集成電路（IC）的DSP（數(shù)字信號處理器）規(guī)格書PDF中文資料

ADSP-21061KS-133屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADSP-21061KS-133DSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應(yīng)用。

ADSP-2106x SHARC? DSP Microcomputer Family

GENERAL DESCRIPTION

The ADSP-21061 SHARC—Super Harvard Architecture Computer—is a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-21061 SHARC is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dualported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

SUMMARY

High performance signal processor for communications, graphics, and imaging applications

Super Harvard Architecture

Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier, ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip

Integrated multiprocessing features

KEY FEATURES—PROCESSOR CORE

50 MIPS, 20 ns instruction rate, single-cycle instruction execution

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse addressing

Efficient program sequencing with zero-overhead looping: single-cycle loop setup

IEEE JTAG Standard 1149.1 test access port and on-chip emulation

32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format

240-lead MQFP package, thermally enhanced MQFP, 225-ball plastic ball grid array (PBGA)

Lead (Pb) free packages. For more information, see Ordering Guide on Page 52.