ADP1752集成電路（IC）的穩(wěn)壓器-線性規(guī)格書PDF中文資料

ADP1752屬于集成電路（IC）的穩(wěn)壓器-線性。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADP1752穩(wěn)壓器 - 線性線性穩(wěn)壓器用于提供穩(wěn)定的輸出電壓，無論負(fù)載電流、輸入電壓或環(huán)境因素如何變化，這些輸出電壓通常都要保持不變。它們的工作原理要求輸入電壓維持在高于所需的輸出電壓，而且要超出某個最小量，并且在工作時會將輸入端的任何多余電壓轉(zhuǎn)換為熱量。對于大多數(shù)應(yīng)用而言，雖然這種穩(wěn)壓器的效率低于開關(guān)模式的穩(wěn)壓器，但它們通常更適合對噪聲高度敏感的應(yīng)用。

GENERAL DESCRIPTION

The ADP1752/ADP1753 are low dropout (LDO) CMOS linear regulators that operate from 1.6 V to 3.6 V and provide up to 800 mA of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced proprietary architecture, they provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7 μF ceramic output capacitor.

FEATURES

Maximum output current: 0.8 A

Input voltage range: 1.6 V to 3.6 V

Low shutdown current: <2 μA

Very low dropout voltage: 70 mV @ 0.8 A load

Initial accuracy: ±1

Accuracy over line, load, and temperature: ±2

7 fixed output voltage options with soft start 0.75 V to 2.5 V (ADP1752)

Adjustable output voltage option with soft start 0.75 V to 3.3 V (ADP1753)

High PSRR 65 dB @ 1 kHz 65 dB @ 10 kHz 54 dB @ 100 kHz

23 μV rms at 0.75 V output

Stable with small 4.7 μF ceramic output capacitor

Excellent load and line transient response

Current-limit and thermal overload protection

Power-good indicator

Logic-controlled enable

Reverse current protection

APPLICATIONS

Server computers

Memory components

Telecommunications equipment

Network equipment

DSP/FPGA/microprocessor supplies

Instrumentation equipment/data acquisition systems