ADN4605_V01中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

DC to 4.25 Gbps per port NRZ data rate Adjustable receive equalization

3 dB, 6 dB, or 12 dB boost

Compensates over 40 inches of FR4 at 4.25 Gbps Adjustable transmit preemphasis/deemphasis

Programmable boost and output level

Compensates over 40 inches of FR4 at 4.25 Gbps Low power

105 mW per channel at 2.5 V (400 mV p-p differential output level swing)

40 × 40, fully differential, nonblocking array

Double rank connection programming with dual maps Low jitter, typically <25 ps Flexible 2.5 V to 3.3 V supply range

DC- or ac-coupled differential PECL/CML inputs

Differential CML outputs

Per-lane polarity inversion for routing ease 50 Ω on-chip I/O termination with disable feature Supports 8b10b, scrambled or uncoded NRZ data Serial (I?C slave or SPI) control interface Parallel control interface

APPLICATIONS

Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI) Fiber optic network switching

High speed serial backplane routing to OC-48 with FEC XAUI, 4x Fibre Channel, Infiniband?, and GbE over backplane

Data storage networks