ADN2812ACPZ-RL集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)規(guī)格書PDF中文資料

ADN2812ACPZ-RL屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADN2812ACPZ-RL應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。

GENERAL DESCRIPTION

The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40°C to +85°C ambient temperature, unless otherwise noted.

FEATURES

Serial data input: 12.3 Mb/s to 2.7 Gb/s

Exceeds SONET requirements for jitter transfer/

generation/tolerance

Quantizer sensitivity: 6 mV typical

Adjustable slice level: ±100 mV

Patented clock recovery architecture

Loss of signal (LOS) detect range: 3 mV to 15 mV

Independent slice level adjust and LOS detector

No reference clock required

Loss of lock indicator

I2C interface to access optional features

Single-supply operation: 3.3 V

Low power: 750 mW typical

5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates

Fibre Channel, 2× Fibre Channel, GbE, HDTV

WDM transponders

Regenerators/repeaters

Test equipment

Broadband cross-connects and routers