ADAU1979WBCPZRL中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

Four 4.5 V rms (typical) differential inputs

On-chip phase-locked loop (PLL) for master clock

Low electromagnetic interference (EMI) design

109 dB (typical) analog-to-digital converter (ADC)

dynamic range

Total harmonic distortion + noise (THD + N): ?95 dB

(typical)

Selectable digital high-pass filter

24-bit stereo ADC with 8 kHz to 192 kHz sample rates

Digital volume control with autoramp function

I2C/SPI controllable for flexibility

Software-controllable clickless mute

Software power-down

Right justified, left justified, I2S, and TDM modes

Master and slave operation modes

40-lead LFCSP

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Active noise cancellation systems