ADAU1701JSTZ-RL集成電路（IC）的DSP（數(shù)字信號(hào)處理器）規(guī)格書PDF中文資料

ADAU1701JSTZ-RL屬于集成電路（IC）的DSP（數(shù)字信號(hào)處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADAU1701JSTZ-RLDSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。

GENERAL DESCRIPTION

The ADAU1701 is a complete audio system-on-a-chip including a 28/56-bit audio DSP, ADCs and DACs, and microcontroller-like control interfaces. Signal processing includes equalization, crossover, bass enhancement, multiband dynamics processing, delay compensation, speaker

compensation, and stereo image widening. These algorithms can be used to compensate for the real-world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of perceived audio quality.

FEATURES

28/56-bit, 50 MHz digital audio processor

Stereo ADC: 100 dB SNR and -80 dB THD+N

4-channel DAC: 104 dB SNR and -90 dB THD+N

Complete stand-alone operation

? Self-boot from serial EEPROM

? Auxiliary ADC with four-input mux for analog control

? GPIOs for digital controls and outputs

Fully programmable with SigmaStudio? graphical tool

28-bit × 28-bit multiplier with 56-bit accumulator for full double precision processing

Clock Oscillator for generating master clock from crystal

PLL for generating master clock from 64 × fS, 256 × fS, 384 × fS, or 512 × fSclocks

Flexible serial data I/O ports with I2S compatible, left justified, right-justified, and TDM modes

Sampling rates up to 192 kHz supported

On-chip voltage regulator for compatibility with 3.3 V systems

48-lead LQFP plastic package