AD9956開發(fā)板套件編程器的評(píng)估演示板及套件規(guī)格書PDF中文資料

AD9956屬于開發(fā)板套件編程器的評(píng)估演示板及套件。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9956評(píng)估和演示板及套件該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過(guò)驗(yàn)證的實(shí)施環(huán)境中評(píng)估某些重點(diǎn)器件的性能或特性。評(píng)估方法通常有完善的文檔說(shuō)明，并且視乎具體情況由評(píng)估軟件提供支持。產(chǎn)品通常由印刷電路板組成，板上已裝有重點(diǎn)器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對(duì)于數(shù)量特別多或類別獨(dú)特的器件類別(如 ADC、DAC 和開關(guān)模式電源)，評(píng)估平臺(tái)可組合為一個(gè)單獨(dú)的產(chǎn)品系列。

FEATURES

400 MSPS internal DDS clock speed

48-bit frequency tuning word

14-bit programmable phase offset

Integrated 14-bit DAC

Excellent dynamic performance

Phase noise ≤ 135 dBc/Hz @ 1 KHz offset

?80 dB SFDR @ 160 MHz (±100 KHz offset IOUT)

25 Mb/s write-speed serial I/O control

200 MHz phase frequency detector inputs

655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)

Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)

8 phase/frequency profiles

1.8 V supply for device operation

3.3 V supply for I/O and charge pump

Software controlled power-down

48-lead LFCSP package

Automatic linear frequency sweeping capability (in DDS)

Programmable charge pump current (up to 4 mA)

Phase modulation capability

Multichip synchronization

Dual-mode PLL lock detect

655 MHz CML-mode PECL-compliant driver

APPLICATIONS

Agile LO frequency synthesis

FM chirp source for radar and scanning systems

Automotive radars

Test and measurement equipment

Acousto-optic device drivers