AD9912集成電路（IC）的直接數(shù)字合成（DDS）規(guī)格書(shū)PDF中文資料

AD9912屬于集成電路（IC）的直接數(shù)字合成（DDS）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9912直接數(shù)字合成（DDS）直接數(shù)字合成 (DDS) 用于由數(shù)字信號(hào)生成不同頻率的模擬波形。在必須大范圍掃描的無(wú)線系統(tǒng)中可用于頻率控制。主時(shí)鐘頻率有 5MHz、16MHz、16.776MHz、25MHz、50MHz、75MHz、125MHz、180MHz、200MHz、250MHz、300MHz、400MHz、500MHz、1GHz、2.5GHz 和 3GHz，分辨率為 10 b、12 b 或 14 b。

GENERAL DESCRIPTION

The AD9912 is a direct digital synthesizer (DDS) that features an integrated 14-bit digital-to-analog converter (DAC). The AD9912 features a 48-bit frequency tuning word (FTW) that can synthesize frequencies in step sizes no larger than 4 μHz. Absolute frequency accuracy can be achieved by adjusting the DAC system clock.The AD9912 also features an integrated system clock phase locked loop (PLL) that allows for system clock inputs as low as 25 MHz.

FEATURES

1 GSPS internal clock speed (up to 400 MHz output directly)

Integrated 1 GSPS 14-bit DAC

48-bit frequency tuning word with 4 μHz resolution

Differential HSTL comparator

Flexible system clock input accepts either crystal or external reference clock

On-chip low noise PLL REFCLK multiplier

2 SpurKiller channels

Low jitter clock doubler for frequencies up to 750 MHz

Single-ended CMOS comparator; frequencies of <150 MHz

Programmable output divider for CMOS output

Serial I/O control

Excellent dynamic performance

Software controlled power-down

Available in two 64-lead LFCSP packages

Residual phase noise @ 250 MHz

10 Hz offset: ?113 dBc/Hz

1 kHz offset: ?133 dBc/Hz

100 kHz offset: ?153 dBc/Hz

40 MHz offset: ?161 dBc/Hz

APPLICATIONS

Agile LO frequency synthesis

Low jitter, fine tune clock generation

Test and measurement equipment

Wireless base stations and controllers

Secure communications

Fast frequency hopping