AD9650-65EBZ開發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9650-65EBZ屬于開發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9650-65EBZ評(píng)估板 - 模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器 (ADC) 評(píng)估板是預(yù)裝有元器件的電路板，用于提供特定 ADC 或器件工作實(shí)例。特定板上的 A/D 轉(zhuǎn)換器數(shù)量從 3 到 32 不等，每秒采樣率從 2.5 kHz 到 26 GHz 不等，輸入電壓范圍從 0 到 8 Vp-p。

GENERAL DESCRIPTION

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

FEATURES

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

SNR

82 dBFS at 30 MHz input and 105 MSPS data rate

83 dBFS at 9.7 MHz input and 25 MSPS data rate

SFDR

90 dBc at 30 MHz input and 105 MSPS data rate

95 dBc at 9.7 MHz input and 25 MSPS data rate

Low power

328 mW per channel at 105 MSPS

119 mW per channel at 25 MSPS

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

Analog input range of 2.7 V p-p

Optional on-chip dither

Integrated ADC sample-and-hold inputs

Differential analog inputs with 500 MHz bandwidth

ADC clock duty cycle stabilizer

APPLICATIONS

Industrial instrumentation

X-Ray, MRI, and ultrasound equipment

High speed pulse acquisition

Chemical and spectrum analysis

Direct conversion receivers

Multimode digital receivers

Smart antenna systems

General-purpose software radios