GENERAL DESCRIPTION

The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs.

The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate up to a frequency of 3.6 GHz. All outputs share a common divider that can provide a division of 1 to 6.

FEATURES

Integrated ultralow noise synthesizer

8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC

output or 2 CMOS SYNC outputs

2 differential reference inputs and 1 single-ended reference

input

APPLICATIONS

LTE and multicarrier GSM base stations

Clocking high speed ADCs, DACs

ATE and high performance instrumentation

40/100 Gb/sec OTN line side clocking

Cable/DOCSIS CMTS clocking

Test and measurement

AD9525BCPZ屬于集成電路（IC） > 時鐘發(fā)生器，PLL，頻率合成器。亞德諾半導體技術有限公司制造生產的AD9525BCPZ時鐘發(fā)生器，PLL，頻率合成器時鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時脈沖，這些器件包括計算機、微控制器、數據通信系統和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅動器、分頻器、倍頻器、多路復用器、合成器、扇出分配器和預分頻器。