AD9516-3/PCBZ開發(fā)板套件編程器的評估演示板及套件規(guī)格書PDF中文資料

AD9516-3/PCBZ屬于開發(fā)板套件編程器的評估演示板及套件。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9516-3/PCBZ評估和演示板及套件該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過驗(yàn)證的實(shí)施環(huán)境中評估某些重點(diǎn)器件的性能或特性。評估方法通常有完善的文檔說明，并且視乎具體情況由評估軟件提供支持。產(chǎn)品通常由印刷電路板組成，板上已裝有重點(diǎn)器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對于數(shù)量特別多或類別獨(dú)特的器件類別(如 ADC、DAC 和開關(guān)模式電源)，評估平臺可組合為一個(gè)單獨(dú)的產(chǎn)品系列。

GENERAL DESCRIPTION

The AD9516-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.

FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 1.75 GHz to 2.25 GHz

External VCO/VCXO to 2.4 GHz optional

1 differential or 2 single-ended reference inputs

Reference monitoring capability

Automatic revertive and manual reference

switchover/holdover modes

Accepts LVPECL, LVDS, or CMOS references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

6 pairs of 1.6 GHz LVPECL outputs

Each output pair shares a 1-to-32 divider with coarse

phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs of <10 ps

4 pairs of 800 MHz LVDS clock outputs

Each output pair shares two cascaded 1-to-32 dividers

with coarse phase delay

Additive output jitter: 275 fs rms

Fine delay adjust (Δt) on each LVDS output

Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up

Manual output synchronization available

64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation