GENERAL DESCRIPTION

The AD835 is a complete four-quadrant, voltage output analog multiplier, fabricated on an advanced dielectrically isolated complementary bipolar process. It generates the linear product of its X and Y voltage inputs with a ?3 dB output bandwidth of 250 MHz (a small signal rise time of 1 ns). Full-scale (?1 V to +1 V) rise to fall times are 2.5 ns (with a standard RL of 150 Ω), and the settling time to 0.1 under the same conditions is typically 20 ns.

Its differential multiplication inputs (X, Y) and its summing input (Z) are at high impedance. The low impedance output voltage (W) can provide up to ±2.5 V and drive loads as low as 25 Ω. Normal operation is from ±5 V supplies.

Though providing state-of-the-art speed, the AD835 is simple to use and versatile. For example, as well as permitting the addition of a signal at the output, the Z input provides the means to operate the AD835 with voltage gains up to about ×10. In this capacity, the very low product noise of this multiplier (50 nV/√Hz) makes it much more useful than earlier products.

The AD835 is available in an 8-lead PDIP package (N) and an 8-lead SOIC package (R) and is specified to operate over the ?40°C to +85°C industrial temperature range.

FEATURES

Simple: basic function is W = XY + Z

Complete: minimal external components required

Very fast: Settles to 0.1 of full scale (FS) in 20 ns

DC-coupled voltage output simplifies use

High differential input impedance X, Y, and Z inputs

Low multiplier noise: 50 nV/√Hz

APPLICATIONS

Very fast multiplication, division, squaring

Wideband modulation and demodulation

Phase detection and measurement

Sinusoidal frequency doubling

Video gain control and keying

Voltage-controlled amplifiers and filters

AD835AR屬于集成電路（IC） > 模擬乘法器、除法器。亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD835AR模擬乘法器、除法器模擬乘法器獲取兩個(gè)或更多模擬信號，并產(chǎn)生這些信號的乘積或乘積之和的輸出。此類電路可用于實(shí)現(xiàn)相關(guān)計(jì)算功能，例如計(jì)算平方（對兩個(gè)輸入都施加相同的信號）和平方根。應(yīng)用可能包括可變增益放大器、環(huán)形調(diào)制器、乘積檢測器、混頻器、增益控制、真 RMS 轉(zhuǎn)換器和脈沖幅度調(diào)制器 (PAM)。