AD8156集成電路（IC）的信號(hào)開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

AD8156屬于集成電路（IC）的信號(hào)開關(guān)多路復(fù)用器解碼器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD8156信號(hào)開關(guān)，多路復(fù)用器，解碼器邏輯型信號(hào)開關(guān)、多路復(fù)用器和編碼器 IC 可用于對(duì)以數(shù)字格式表示數(shù)據(jù)的電信號(hào)進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號(hào)的類似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無窮變化量。

GENERAL DESCRIPTION

The AD8156, a member of the Xstream line of products, is a high speed, fully differential, digital crosspoint switch. The part can function as a 4 × 4 crosspoint switch with double-latched memory, allowing simultaneous updates, or as a dual 2 × 2 with direct output control. The AD8156 has low power dissipation, typically 700 mW on 3.3 V with all outputs and input equalizers active. It operates at any data rate from dc to 6.25 Gbps per port.

Each input channel on the AD8156 has a programmable input equalizer to compensate for signal loss over a backplane.

FEATURES

4 × 4, fully differential, nonblocking array

Configurable for dual 2 × 2 operation

DC to 6.25 Gbps per channel, NRZ data rate

Programmable input equalization compensates for over 40”

of FR-4 at 6.25 Gbps

Multicast and broadcast modes of operation

Programmable output swing

100 mV p-p to 1.6 V p-p differential

Power supply: 3.3 V (±10)

Low power

No EQ: 400 mW typical

Maximum EQ: 700 mW typical

Inputs: ac-coupled or dc-coupled

Wide set of dc-coupled input standards

3.3 V/2.5 V/1.8 V CML or 3.3 V LVPECL

Control: LVTTL- or LVCMOS-compatible

Low additive jitter: 25 ps p-p typical

Low random jitter: 0.8 ps rms

Integrated 50 Ω termination impedance at inputs/outputs

Individual output disable for power savings

49-ball, 8 mm × 8 mm BGA, 1 mm pitch

APPLICATIONS

Backplane equalization

SONET/SDH

Gigabit Ethernet

XAUI

Fibre Channel