AD484M1644VTA-5.5中文資料ETC數(shù)據(jù)手冊PDF規(guī)格書

[Ascend Semiconductor Corporation]

AD484M1644VTA ( 4Mx16 )

Description

The AD484M1644VTA is Synchronous Dynamic Random Access Memory ( SDRAM ) organized as 1,048,756 words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock . The 64Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL .

Features

? Fully synchronous to positive clock edge

? Single 3.3V +/- 0.3V power supply

? LVTTL compatible with multiplexed address

? Industrial temperature available

? Programmable Burst Length ( BL ) - 1,2,4,8 or full page

? Programmable CAS Latency ( CL ) -1, 2 or 3

? Data Mask ( DQM ) for Read/Write masking

? Programmable wrap sequential - Sequential ( BL = 1/2/4/8/full page )

- Interleave ( BL = 1/2/4/8 )

? Burst read with single -bit write operation

? All inputs are sampled at the positive rising edge of the system clock.

? Auto refresh and self refresh

? 4,096 refresh cycles / 64ms