ACT-7000SC-200F24Q中文資料AEROFLEX數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The ACT 7000SC is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high performance 64-bit integer units as well as a high throughput, fully pipelined 64-bit floating point unit.

Features

■ Full militarized QED RM7000 microprocessor

■ Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance

● 150, 200, 210, 225 MHz operating frequency Consult Factory for latest speeds

● MIPS IV Superset Instruction Set Architecture

■ High performance interface (RM52xx compatible)

● 600 MB per second peak throughput

● 75 MHz max. freq., multiplexed address/data

● Supports 1/2 clock multipliers (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)

● IEEE 1149.1 JTAG (TAP) boundary scan

■ Integrated primary and secondary caches - all are 4-way set associative with 32 byte line size

● 16KB instruction

● 16KB data: non-blocking and write-back or write-through

● 256KB on-chip secondary: unified, non-blocking, block writeback

■ MIPS IV instruction set

● Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution

● Floating point combined multiply-add instruction increases performance in signal processing and graphics applications

● Conditional moves reduce branch frequency

● Index address modes (register + register)

■ Embedded supply de-coupling capacitors and additional PLL filter components

■ Integrated memory management unit (ACT52xx compatible)

● Fully associative joint TLB (shared by I and D translations)

● 48 dual entries map 96 pages

● 4 entry DTLB and 4 entry ITLB

● Variable page size (4KB to 16MB in 4x increments)

■ Embedded application enhancements

● Specialized DSP integer Multiply-Accumulate instruction, (MAD/MADU) and three-operand multiply instruction (MUL/U)

● Per line cache locking in primaries and secondary

● Bypass secondary cache option

● I&D Test/Break-point (Watch) registers for emulation & debug

● Performance counter for system and software tuning & debug

● Ten fully prioritized vectored interrupts - 6 external, 2 internal, 2 software

● Fast Hit-Writeback-Invalidate and Hit-Invalidate cache operations for efficient cache management

■ High-performance floating point unit - 600 M FLOPS maximum

● Single cycle repeat rate for common single-precision operations and some double-precision operations

● Single cycle repeat rate for single-precision combined multiplyadd operations

● Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations

■ Fully static CMOS design with dynamic power down logic

● Standby reduced power mode with WAIT instruction

● 4 watts typical @ 2.5V Int., 3.3V I/O, 200MHz

■ 208-lead CQFP, cavity-up package (F17)

■ 208-lead CQFP, inverted footprint (F24), with the same pin rotation as the commercial QED RM5261