A54SX32A-PQG208A集成電路（IC）的FPGA（現(xiàn)場可編程門陣列）規(guī)格書PDF中文資料

Features

? Hot-Swap Compliant I/Os

? Power-Up/Down Friendly (No Sequencing Required for Supply Voltages)

? 66 MHz PCI Compliant

? Nonvolatile, Single-Chip Solution

? Configurable I/O Support for 3.3 V / 5 V PCI, 5 V TTL, 3.3 V LVTTL, 2.5 V LVCMOS2

? 2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with 5 V Input Tolerance and 5 V Drive Strength

? Devices Support Multiple Temperature Grades

? Configurable Weak-Resistor Pull-Up or Pull-Down for I/O at Power-Up

? Individual Output Slew Rate Control

? Up to 100 Resource Utilization and 100 Pin Locking

? Deterministic, User-Controllable Timing

? Unique In-System Diagnostic and Verification Capability with Silicon Explorer II

? Boundary-Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)

? Actel Secure Programming Technology with FuseLock? Prevents Reverse Engineering and Design Theft

Leading-Edge Performance

? 250 MHz System Performance

? 350 MHz Internal Performance

Specifications

? 12,000 to 108,000 Available System Gates

? Up to 360 User-Programmable I/O Pins

? Up to 2,012 Dedicated Flip-Flops

? 0.22 μ / 0.25 μ CMOS Process Technology