9ZX21901D集成電路（IC）的應用特定時鐘/定時規(guī)格書PDF中文資料

Features

? Fixed feedback path; 0ps input-to-output delay

? 9 Selectable SMBus addresses; multiple devices can share

same SMBus segment

? 8 dedicated OE# pins; hardware control of outputs

? PLL or bypass mode; PLL can dejitter incoming clock

? Selectable PLL BW; minimizes jitter peaking in downstream PLL's

? Hardware or software control of PLL operating mode;

change mode with software mode does not need power cycle

? Spread spectrum compatible; tracks spreading input clock

for EMI reduction

? SMBus Interface; unused outputs can be disabled

? 100MHz and 133.33MHz PLL mode; legacy QPI support

? 72-QFN 10 x 10 mm package; small board footprint