9DBU0631集成電路（IC）的應用特定時鐘/定時規(guī)格書PDF中文資料

Description

The 9DBU0631 is a member of IDT's 1.5V Ultra-Low-Power

(ULP) PCIe family. The device has 6 output enables for clock

management and 3 selectable SMBus addresses.

Features/Benefits

? LP-HCSL outputs; save 12 resistors compared to standard

HCSL outputs

? 46mW typical power consumption in PLL mode; eliminates

thermal concerns

? Outputs can optionally be supplied from any voltage

between 1.05 and 1.5V; maximum power savings

? Spread Spectrum (SS) compatible; allows SS for EMI

reduction

? OE# pins; support DIF power management

? HCSL-compatible differential input; can be driven by

common clock sources

? SMBus-selectable features; optimize signal integrity to

application

? slew rate for each output

? differential output amplitude

? Pin/SMBus selectable PLL bandwidth and PLL Bypass;

optimize PLL to application

? Outputs blocked until PLL is locked; clean system start-up

? Device contains default configuration; SMBus interface not

required for device control

? 3.3V tolerant SMBus interface works with legacy controllers

? Three selectable SMBus addresses; multiple devices can

easily share an SMBus segment

? Space saving 40-pin 5x5mm VFQFPN; minimal board

space