9DBL0853ANDGI中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? LOS open-drain output indicates loss of input clock

? 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4

resistors per output pair

? 9DBLxx4x devices provide integrated 100Ω terminations

? 9DBLxx5x devices provide integrated 85Ω terminations

? See AN-891 for easy coupling to other logic families

? Spread-spectrum compatible

? Dedicated OE# pin for each output

? 1MHz to 200MHz operation in fan-out mode

? 3 selectable SMBus addresses

? Extensive SMBus-selectable features allow optimization to

customer requirements

? SMBus interface not required for device operation

? -40°C to +85°C operating temperature range

? Space-saving 4 × 4 mm 24-VFQFPN to 6 × 6 mm 48-VFQFPN

packages (see Ordering Information table for details)