89HPES8T5集成電路（IC）的專用規(guī)格書PDF中文資料

Features

◆ High Performance PCI Express Switch

– Eight 2.5 Gbps PCI Express lanes

– Five switch ports

– Upstream port is x4

– Downstream ports are x1

– Low-latency cut-through switch architecture

– Support for Max Payload Size up to 256 bytes

– One virtual channel

– Eight traffic classes

– PCI Express Base Specification Revision 1.1 compliant

◆ Flexible Architecture with Numerous Configuration Options

– Automatic lane reversal on all ports

– Automatic polarity inversion on all lanes

– Ability to load device configuration from serial EEPROM

◆ Legacy Support

– PCI compatible INTx emulation

– Bus locking

◆ Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

queueing

– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B

encoder/decoder (no separate transceivers needed)

◆ Reliability, Availability, and Serviceability (RAS) Features

– Supports ECRC and Advanced Error Reporting

– Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O

– Compatible with Hot-Plug I/O expanders used on PC and

server motherboards

◆ Power Management

– Utilizes advanced low-power design techniques to achieve low

typical power consumption

– Supports PCI Power Management Interface specification

(PCI-PM 1.1)

? Supports device power management states: D0, D3hot and

D3cold

– Unused SerDes are disabled