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89HPES32NT8BG2中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

89HPES32NT8BG2
廠商型號(hào)

89HPES32NT8BG2

功能描述

32-Lane 8-Port PCIe? Gen2 System Interconnect Switch

文件大小

530.2 Kbytes

頁面數(shù)量

36

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-6-22 16:11:00

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89HPES32NT8BG2規(guī)格書詳情

Features

? High Performance Non-Blocking Switch Architecture

– 32-lane, 8-port PCIe switch with flexible port configuration

– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

Gen1 operation

– Delivers up to 32 GBps (256 Gbps) of switching capacity

– Supports 128 Bytes to 2 KB maximum payload size

– Low latency cut-through architecture

– Supports one virtual channel and eight traffic classes

? Port Configurability

– Eight x4 switch ports

? Adjacent x4 ports can be merged to achieve x8 port widths

– Automatic per port link width negotiation

(x8 --> x4 --> x2 --> x1)

– Crosslink support

– Automatic lane reversal

– Per lane SerDes configuration

? De-emphasis

? Receive equalization

? Drive strength

? Innovative Switch Partitioning Feature

– Supports up to 8 fully independent switch partitions

– Logically independent switches in the same device

– Configurable downstream port device numbering

– Supports dynamic reconfiguration of switch partitions

? Dynamic port reconfiguration — downstream, upstream,

non-transparent bridge

? Dynamic migration of ports between partitions

? Movable upstream port within and between switch partitions

? Non-Transparent Bridging (NTB) Support

– Supports up to 8 NT endpoints per switch, each endpoint can

communicate with other switch partitions or external PCIe

domains or CPUs

– 6 BARs per NT Endpoint

? Bar address translation

Product Description

With Non-Transparent Bridging functionality and innovative Switch

Partitioning feature, the PES32NT8BG2 allows true multi-host or multiprocessor communications in a single device. Integrated DMA controllers enable high-performance system design by off-loading data transfer

operations across memories from the processors. Each lane is capable

of 5 GT/s link speed in both directions and is fully compliant with PCI

Express Base Specification 2.1.

A non-transparent bridge (NTB) is required when two PCI Express

domains need to communicate to each other. The main function of the

NTB block is to initialize and translate addresses and device IDs to

allow data exchange across PCI Express domains. The major functionalities of the NTB block are summarized in Table 1.

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IDT
2402+
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8324
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16+
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2500
進(jìn)口原裝現(xiàn)貨/價(jià)格優(yōu)勢!
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500000
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一級(jí)代理 原裝正品假一罰十價(jià)格優(yōu)勢長期供貨
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IDT
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23+
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