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874328I-01中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

874328I-01
廠商型號(hào)

874328I-01

功能描述

2.5V Differential Clock Divider/Buffer

文件大小

370.22 Kbytes

頁(yè)面數(shù)量

23 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-5-14 16:06:00

人工找貨

874328I-01價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨

874328I-01規(guī)格書詳情

General Description

The 874328I-01 is a high-performance differential ÷1 and ÷4 clock

divider and fanout buffer. The device is designed for the

frequency-division and signal fanout of high-frequency, low

phase-noise clock signals. The differential input signal is frequency

divided by ÷1 and ÷4. Three LVPECL and three LVDS output banks

are provided with a total of twenty differential outputs. The

874328I-01 is characterized to operate from a 2.5V power supply.

Guaranteed output-to-output and part-to-part skew characteristics

make the 874328I-01 ideal for those clock distribution applications

demanding well-defined performance and repeatability.

Features

? One differential input LVPECL reference clock

? Differential pair can accept the following differential input

levels: LVPECL, LVDS, CML, SSTL

? Integrated input termination resistors

? One bank of three LVPECL outputs (÷1 frequency-divided)

? One bank of three LVPECL outputs (÷4 frequency-divided)

? One bank of two LVPECL outputs (÷4 frequency-divided)

? Two banks of three LVDS outputs (÷4 frequency-divided)

? One bank of six LVDS outputs (÷4 frequency-divided)

? Total of twenty differential clock outputs

? Maximum input frequency: 650MHz

? Maximum output frequency: 650MHz (÷1 outputs)

? Maximum output frequency: 162.5MHz (÷4 outputs)

? LVCMOS interface levels for all control inputs

? Output skew: 70ps (maximum)

? Part-to-part skew: 250ps (maximum)

? Full 2.5V supply voltage

? Available in lead-free (RoHS 6) package

? -40°C to 85°C ambient operating temperature

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
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