8732-01中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Ten differential 3.3V LVPECL outputs

? Selectable differential CLK0, nCLK0 or

LVCMOS/LVTTL CLK1 inputs

? CLK0, nCLK0 supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

? CLK1 accepts the following input levels:

LVCMOS or LVTTL

? Maximum output frequency: 350MHz

? VCO range: 250MHz to 700MHz

? External feedback for “zero delay” clock regeneration

with confi gurable frequencies

? Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum)

CLK1, 80ps (maximum)

? Output skew: 150ps (maximum)

? Static phase offset: -150ps to 150ps

? Lead-Free package fully RoHS compliant