74VHC125集成電路（IC）的緩沖器驅動器接收器收發(fā)器規(guī)格書PDF中文資料

74VHC125屬于集成電路（IC）的緩沖器驅動器接收器收發(fā)器。由意法半導體集團制造生產(chǎn)的74VHC125緩沖器，驅動器，接收器，收發(fā)器邏輯緩沖器、驅動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。

DESCRIPTION

The 74VHC125 is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

The device requires the 3-STATE control input G to be set high to place the output in to the high impedance state.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 4 μA (MAX.) at TA=25°C

■ HIGH NOISE IMMUNITY:

VNIH = VNIL = 28 VCC (MIN.)

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8mA (MIN)

■ BALANCED PROPAGATION DELAYS:

tPLH = tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: VOLP = 0.8V (MAX.)