74LVT273中文資料恩XP數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General description

The 74LVT273 is a high-performance BiCMOS product designed for VCC operation at 3.3 V.

This device has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where only the true output is required and the CP and MR are common elements.

Features

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock and asynchronous master reset

■ Input and output interface capability to systems at 5 V supply

■ TTL input and output switching levels

■ Input and output interface capability to systems at 5 V supply

■ Output capability: +64 mA/?32 mA

■ Latch-up protection

◆ JESD78 Class II exceeds 500 mA

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs

■ Live insertion/extraction permitted

■ Power-up reset

■ No bus current loading when output is tied to 5 V bus