74LVQ573T集成電路（IC）的鎖存器規(guī)格書PDF中文資料

74LVQ573T屬于集成電路（IC）的鎖存器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的74LVQ573T鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號有效時反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時改變。

DESCRIPTION

The LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V

■ COMPATIBLEWITH TTL OUTPUTS

■ LOW POWER DISSIPATION:

ICC =4 μA (MAX.) at TA = 25 °C

■ LOW NOISE:

VOLP = 0.5 V (TYP.) at VCC = 3.3V

■ 75? TRANSMISSIONLINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24 mA (MIN)

■ PCI BUS LEVELSGUARANTEED AT 24mA

■ BALANCEDPROPAGATIONDELAYS: tPLH ? tPHL

■ OPERATING VOLTAGERANGE:

VCC (OPR)= 2V to 3.6V (1.2VData Retention)

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573

■ IMPROVED LATCH-UP IMMUNITY