1. General description

The 74LVC2G04 is a dual inverter. Inputs can be driven from either 3.3 V or 5 V devices. This

feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 5.5 V

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? ±24 mA output drive (VCC = 3.0 V)

? CMOS low power dissipation

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 250 mA

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? JESD36 (4.6 V to 5.5 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from ?40 °C to +85 °C and ?40 °C to +125 °C.

74LVC2G04GN屬于集成電路（IC） > 門和反相器。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74LVC2G04GN門和反相器邏輯柵極和逆變器系列中的產(chǎn)品對(duì)單個(gè)邏輯信號(hào)執(zhí)行基本邏輯運(yùn)算（例如 AND、NOT、OR 等）。與觸發(fā)器不同，它們不能夠存儲(chǔ)信息，不會(huì)對(duì)提供給其輸入的信號(hào)立即做出響應(yīng)。雖然早就被集成電路實(shí)施形式所取代，以用于實(shí)現(xiàn)復(fù)雜功能，但分立柵極仍可在僅需要非常簡(jiǎn)單邏輯功能的情況下使用。