1. General description

The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets

the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the

flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This

feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 5.5 V

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? CMOS low power dissipation

? ±24 mA output drive (VCC = 3.0 V)

? Direct interface with TTL levels

? Latch-up performance exceeds 250 mA

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? JESD36 (4.5 V to 5.5 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C.

74LVC1G79GM屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74LVC1G79GM觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類(lèi)型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。