74LVC1G57GN集成電路（IC）的門反相器-多功能可配置規(guī)格書PDF中文資料

廠商型號	74LVC1G57GN
參數(shù)屬性	74LVC1G57GN 封裝/外殼為6-XFDFN；包裝為卷帶（TR）；類別為集成電路（IC）的門反相器-多功能可配置；產(chǎn)品描述：IC CONFIG MULTI-FUNC GATE 6XSON
功能描述	Low-power configurable multiple function gate
絲印標識	YC
封裝外殼	SOT1115 / 6-XFDFN
文件大小	269.24 Kbytes
頁面數(shù)量	18 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-2-22 22:59:00
人工找貨	74LVC1G57GN價格和庫存，歡迎聯(lián)系客服免費人工找貨

1. General description

The 74LVC1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device

can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter

and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Inputs can be

driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators

in mixed 3.3 V and 5 V environments.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 5.5 V

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? ±24 mA output drive (VCC = 3.0 V)

? CMOS low power dissipation

? Latch-up performance exceeds 250 mA

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8B/JESD36 (2.7 V to 3.6 V).

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C.