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74LV123

Dual retriggerable monostable multivibrator with reset

DESCRIPTION The74LV123isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewiththe74HC/HCT123. FEATURES ?OptimizedforLowVoltageapplications:1.0to5.5V ?AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V ?TypicalVOLP(outputgroundbounce)=0.8V@

PHIPhilips Semiconductors

飛利浦荷蘭皇家飛利浦

PHI

74LV123

Dual retriggerable monostable multivibrator with reset

Generaldescription The74LV123isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewiththe74HC123;74HCT123. Featuresandbenefits ■Optimizedforlow-voltageapplications:1.0Vto5.5V ■AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V ■Typicaloutp

74LV123

Dual retriggerable monostable multivibrator with reset

1.Generaldescription The74LV123isadualretriggerablemonostablemultivibratorwithreset.Thebasicoutputpulse widthisprogrammedbyselectionofexternalcomponents(REXTandCEXT).Oncetriggeredthis basicpulsewidthmaybeextendedbyretriggeringeitheroftheedgetriggeredinpu

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國)有限公司

74LV123

Dual retriggerable monostable multivibrator with reset Rev. 7 ??12 December 2011

PHIPhilips Semiconductors

飛利浦荷蘭皇家飛利浦

PHI

74LV123BQ

Dual retriggerable monostable multivibrator with reset

Generaldescription The74LV123isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewiththe74HC123;74HCT123. Featuresandbenefits ■Optimizedforlow-voltageapplications:1.0Vto5.5V ■AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V ■Typicaloutp

74LV123BQ

Dual retriggerable monostable multivibrator with reset

1.Generaldescription The74LV123isadualretriggerablemonostablemultivibratorwithreset.Thebasicoutputpulse widthisprogrammedbyselectionofexternalcomponents(REXTandCEXT).Oncetriggeredthis basicpulsewidthmaybeextendedbyretriggeringeitheroftheedgetriggeredinpu

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國)有限公司

74LV123D

Dual retriggerable monostable multivibrator with reset

DESCRIPTION The74LV123isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewiththe74HC/HCT123. FEATURES ?OptimizedforLowVoltageapplications:1.0to5.5V ?AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V ?TypicalVOLP(outputgroundbounce)=0.8V@

PHIPhilips Semiconductors

飛利浦荷蘭皇家飛利浦

PHI

74LV123D

Dual retriggerable monostable multivibrator with reset

Generaldescription The74LV123isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewiththe74HC123;74HCT123. Featuresandbenefits ■Optimizedforlow-voltageapplications:1.0Vto5.5V ■AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V ■Typicaloutp

74LV123D

Dual retriggerable monostable multivibrator with reset

1.Generaldescription The74LV123isadualretriggerablemonostablemultivibratorwithreset.Thebasicoutputpulse widthisprogrammedbyselectionofexternalcomponents(REXTandCEXT).Oncetriggeredthis basicpulsewidthmaybeextendedbyretriggeringeitheroftheedgetriggeredinpu

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國)有限公司

74LV123D

Dual retriggerable monostable multivibrator with reset; ? Optimized for low-voltage applications: 1.0 V to 5.5 V\n? Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V\n? Typical output ground bounce: < 0.8 V at VCC = 3.3 V and Tamb = 25 ℃\n? Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 ℃\n? DC triggered from active HIGH or active LOW inputs\n? Retriggerable for very long pulses up to 100 % duty factor\n? Direct reset terminates output pulses\n? Schmitt-trigger action on all inputs except for the reset input\n;

The 74LV123 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC123; 74HCT123. It is a dual retriggerable monostable multivibrator which uses three methods to control the output pulse width:\nThe basic pulse time is programmed by the selection of an external resistor (REXT) and capacitor (CEXT).Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired.Alternatively, an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering. Schmitt-trigger action in the nA and nB inputs makes the circuit highly tolerant of slower input rise and fall times.\n

NexperiaNexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國)有限公司

技術(shù)參數(shù)

  • VCC (V)：

    1.0?-?5.5

  • Logic switching levels：

    TTL

  • Output drive capability (mA)：

    ± 12

  • tpd (ns)：

    20

  • Power dissipation considerations：

    low

  • Tamb (°C)：

    -40~125

  • Rth(j-a) (K/W)：

    86

  • Ψth(j-top) (K/W)：

    9.0

  • Rth(j-c) (K/W)：

    54

  • Package name：

    DHVQFN16

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7
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更多74LV123供應(yīng)商 更新時(shí)間2025-7-31 10:31:00

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