74HCT374PW集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

廠商型號	74HCT374PW
參數(shù)屬性	74HCT374PW 封裝/外殼為20-TSSOP（0.173"，4.40mm 寬）；包裝為管件；類別為集成電路（IC）的觸發(fā)器；產(chǎn)品描述：IC FF D-TYPE SNGL 8BIT 20TSSOP
功能描述	Octal D-type flip-flop; positive edge-trigger; 3-state
封裝外殼	20-TSSOP（0.173"，4.40mm 寬）
文件大小	259.93 Kbytes
頁面數(shù)量	15 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-28 17:06:00

1. General description

The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs.

The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state

of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH

clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.

Operation of the OE input does not affect the state of the flip-flops. Inputs also include clamp

diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of

VCC.

2. Features and benefits

? Wide supply voltage range from 2.0 to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Input levels:

? For 74HC374: CMOS level

? For 74HCT374: TTL level

? Octal bus interface

? Non-inverting 3-state outputs

? 8-bit positive, edge-triggered register

? Common 3-state output enable input

? Independent register and 3-state buffer operation

? Complies with JEDEC standards

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C