1. General description

The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs

are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8)

is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH.

Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine

parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of

current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

? Word-length easily expanded by cascading

? Generates either odd or even parity for nine data bits

? Wide supply voltage range from 2.0 to 6.0 V

? Input levels:

? For 74HC280: CMOS level

? For 74HCT280: TTL level

? CMOS low power dissipation

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

74HCT280D屬于集成電路（IC） > 奇偶校驗發(fā)生器和校驗器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74HCT280D奇偶校驗發(fā)生器和校驗器邏輯奇偶校驗發(fā)生器和校驗器系列器件是元件級器件，用于評估設(shè)置為 1 的數(shù)字字中的位數(shù)，并另外生成（或評估）一個奇偶校驗位，指示設(shè)置為 1 的字中的位數(shù)是偶數(shù)還是奇數(shù)。此功能通常用作檢測在傳輸過程中可能引入的數(shù)據(jù)錯誤的簡單方法。