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74HCT107DB中文資料飛利浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書
| 廠商型號 |
74HCT107DB |
| 功能描述 | Dual JK flip-flop with reset; negative-edge trigger |
| 文件大小 |
53.67 Kbytes |
| 頁面數(shù)量 |
7 頁 |
| 生產(chǎn)廠商 | NXP Semiconductors |
| 企業(yè)簡稱 |
Philips【飛利浦】 |
| 中文名稱 | 荷蘭皇家飛利浦官網(wǎng) |
| 原廠標(biāo)識 |  |
| 數(shù)據(jù)手冊 | |
| 更新時(shí)間 | 2025-5-15 19:41:00 |
| 人工找貨 | 74HCT107DB價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
74HCT107DB規(guī)格書詳情
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
FEATURES
? Output capability: standard
? ICC category: flip-flops
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
2017+ |
NA |
28562 |
只做原裝正品假一賠十! |
詢價(jià) | |||
PHILIPS |
24+/25+ |
100 |
原裝正品現(xiàn)貨庫存價(jià)優(yōu) |
詢價(jià) | |||
ph |
24+ |
N/A |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價(jià) | ||
Nexperia(安世) |
24+ |
SOP14 |
3238 |
原裝現(xiàn)貨,免費(fèi)供樣,技術(shù)支持,原廠對接 |
詢價(jià) | ||
HARRIS/哈里斯 |
25+ |
IC |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價(jià) | ||
Nexperia(安世) |
24+ |
SOP14 |
7350 |
現(xiàn)貨供應(yīng),當(dāng)天可交貨!免費(fèi)送樣,原廠技術(shù)支持!!! |
詢價(jià) | ||
NXP/恩智浦 |
2020+ |
DIP14 |
5000 |
原裝現(xiàn)貨,優(yōu)勢渠道訂貨假一賠十 |
詢價(jià) | ||
24+ |
5000 |
公司存貨 |
詢價(jià) | ||||
NXP |
22+ |
14SOIC |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
21+ |
PHI |
12588 |
原裝正品,自己庫存 假一罰十 |
詢價(jià) |
