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74HC40103D集成電路(IC)的計(jì)數(shù)器除法器規(guī)格書(shū)PDF中文資料

74HC40103D
廠商型號(hào)

74HC40103D

參數(shù)屬性

74HC40103D 封裝/外殼為16-SOIC(0.154",3.90mm 寬);包裝為管件;類別為集成電路(IC)的計(jì)數(shù)器除法器;產(chǎn)品描述:IC 8BIT SYNC BINARY DOWN 16SOIC

功能描述

8-bit synchronous binary down counter

封裝外殼

16-SOIC(0.154",3.90mm 寬)

文件大小

836.05 Kbytes

頁(yè)面數(shù)量

23 頁(yè)

生產(chǎn)廠商 Nexperia B.V. All rights reserved
企業(yè)簡(jiǎn)稱

NEXPERIA安世

中文名稱

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更新時(shí)間

2025-3-6 17:23:00

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74HC40103D規(guī)格書(shū)詳情

1. General description

The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling

or disabling the clock (CP), for clearing the counter to its maximum count and for

presetting the counter either synchronously or asynchronously. In normal operation, the

counter is decremented by one count on each positive-going transition of the clock (CP).

Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count

output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for

one full clock period. When the synchronous preset enable input (PE) is LOW, data at the

jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition

regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW,

data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of

the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.

When the master reset input (MR) is LOW, the counter is asynchronously cleared to its

maximum count (decimal 255) regardless of the state of any other input. If all control

inputs except TE are HIGH at the time of zero count, the counters will jump to the

maximum count, giving a counting sequence of 256 clock pulses long. Device may be

cascaded using the TE input and the TC output, in either a synchronous or ripple mode.

Inputs include clamp diodes. This enables the use of current limiting resistors to interface

inputs to voltages in excess of VCC.

2. Features and benefits

? Cascadable

? Synchronous or asynchronous preset

? Low-power dissipation

? Complies with JEDEC standard no. 7A

? CMOS input levels

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from ?40 ?C to +80 ?C and from ?40 ?C to +125 ?C

3. Applications

? Divide-by-n counters

? Programmable timers

? Interrupt timers

? Cycle/program counters.

產(chǎn)品屬性

  • 產(chǎn)品編號(hào):

    74HC40103D,653

  • 制造商:

    Nexperia USA Inc.

  • 類別:

    集成電路(IC) > 計(jì)數(shù)器,除法器

  • 系列:

    74HC

  • 包裝:

    管件

  • 邏輯類型:

    二進(jìn)制計(jì)數(shù)器

  • 方向:

  • 復(fù)位:

    異步

  • 定時(shí):

    同步

  • 觸發(fā)器類型:

    正邊沿

  • 工作溫度:

    -40°C ~ 125°C

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    16-SOIC(0.154",3.90mm 寬)

  • 供應(yīng)商器件封裝:

    16-SO

  • 描述:

    IC 8BIT SYNC BINARY DOWN 16SOIC

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