The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC125 noninverting buffer is designed to be used with 3?state memory address drivers, clock drivers, and other bus?oriented systems. The device has four separate output enables that are active?low.

Features

? Output Drive Capability: 15 LSTTL Loads

? Outputs Directly Interface to CMOS, NMOS, and TTL

? Operating Voltage Range: 2.0 to 6.0 V

? Low Input Current: 1.0 μA

? High Noise Immunity Characteristic of CMOS Devices

? In Compliance with the JEDEC Standard No. 7A Requirements

? ESD Performance: HBM  2000 V; Machine Model  200 V

? Chip Complexity: 72 FETs or 18 Equivalent Gates

? These are Pb?Free Devices

74HC125屬于集成電路（IC） > 緩沖器，驅(qū)動器，接收器，收發(fā)器。安森美半導(dǎo)體公司制造生產(chǎn)的74HC125緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。