74F646集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書PDF中文資料

DESCRIPTION

The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both.

FEATURES

? Combines 74F245 and two 74F374 type functions in one chip

? High impedance base inputs for reduced loading (70μA in high and low states)

? Independent registers for A and B buses

? Multiplexed real-time and stored data

? Choice of non-inverting and inverting data paths

? Controlled ramp outputs for 74F646A/74F648A

? 3-state outputs

? 300 mil wide 24-pin slim dip package