74F377A中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書
74F377A規(guī)格書詳情
DESCRIPTION
The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
FEATURES
? High impedance inputs for reduced loading (20μA in Low and High states)
? Ideal for addressable register applications
? Enable for address and data synchronization applications
? Eight edge–triggered D–type flip–flops
? Buffered common clock
? See ’F273A for Master Reset version
? See ’F373 for transparent latch version
? See ’F374 for 3–State version
產(chǎn)品屬性
- 型號(hào)：
74F377A
- 制造商：
PHILIPS
- 制造商全稱：
NXP Semiconductors
- 功能描述：
Octal D-type flip-flop with enable
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
S |
23+ |
DIP |
28533 |
原盒原標(biāo),正品現(xiàn)貨 誠(chéng)信經(jīng)營(yíng) 價(jià)格美麗 假一罰十! |
詢價(jià) | ||
24+ |
N/A |
48000 |
一級(jí)代理-主營(yíng)優(yōu)勢(shì)-實(shí)惠價(jià)格-不悔選擇 |
詢價(jià) | |||
PHI |
23+ |
7.2mm |
3880 |
正品原裝貨價(jià)格低 |
詢價(jià) | ||
PHILIPS |
21+ |
DIP |
9866 |
詢價(jià) | |||
22+ |
5000 |
詢價(jià) | |||||
PHILIPS |
24+ |
SOP-20 |
35200 |
一級(jí)代理/放心采購(gòu) |
詢價(jià) | ||
PHILIPS/飛利浦 |
23+ |
SOIC-20300mil |
5000 |
原廠授權(quán)代理,海外優(yōu)勢(shì)訂貨渠道。可提供大量庫(kù)存,詳 |
詢價(jià) | ||
PHILIPS/飛利浦 |
22+ |
SOP |
11190 |
原裝正品 |
詢價(jià) | ||
PHILIPS |
23+ |
DIP20 |
1029 |
特價(jià)庫(kù)存 |
詢價(jià) | ||
SIG |
1989 |
42 |
原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu) |
詢價(jià) |
