74AVC9112DC集成電路（IC）的時鐘緩沖器驅(qū)動器規(guī)格書PDF中文資料

廠商型號	74AVC9112DC
參數(shù)屬性	74AVC9112DC 封裝/外殼為8-VFSOP（0.091"，2.30mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的時鐘緩沖器驅(qū)動器；產(chǎn)品描述：74AVC9112DC/SOT765/VSSOP8
功能描述	1-to-4 fan-out buffer
絲印標識	Bb
封裝外殼	SOT765-1 / 8-VFSOP（0.091"，2.30mm 寬）
文件大小	205.5 Kbytes
頁面數(shù)量	16 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-2-2 10:30:00

1 General description

The 74AVC9112 is a 1-to-4 fan-out buffer suitable for use in clock distribution. It has

a data input (A), four data outputs (Yn) and an output enable input (OE). VCC can be

supplied at any voltage between 0.8 V and 3.6 V. A HIGH on OE causes all outputs to be

pulled LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors

and enables all outputs.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

The IOFF circuitry disables the output, preventing any damaging backflow current through

the device when it is powered down.

2 Features and benefits

? Wide supply voltage range:

– VCC: 0.8 V to 3.6 V

? Complies with JEDEC standards:

– JESD8-12 (0.8 V to 1.3 V)

– JESD8-11 (0.9 V to 1.65 V)

– JESD8-7 (1.2 V to 1.95 V)

– JESD8-5 (1.8 V to 2.7 V)

– JESD8-B (2.7 V to 3.6 V)

? ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8 kV

– CDM JESD22-C101 exceeds 1000 V

? Maximum data rates:

– 380 Mbit/s (3.3 V)

– 200 Mbit/s (2.5 V)

– 200 Mbit/s (1.8 V)

– 150 Mbit/s (1.5 V)

– 100 Mbit/s (1.2 V)

? Latch-up performance exceeds 100 mA per JESD 78 Class II

? Inputs accept voltages up to 3.6 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C