74AUP2G06GM集成電路（IC）的門反相器規(guī)格書PDF中文資料

74AUP2G06GM屬于集成電路（IC）的門反相器。由安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74AUP2G06GM門和反相器邏輯柵極和逆變器系列中的產(chǎn)品對單個(gè)邏輯信號執(zhí)行基本邏輯運(yùn)算（例如 AND、NOT、OR 等）。與觸發(fā)器不同，它們不能夠存儲信息，不會對提供給其輸入的信號立即做出響應(yīng)。雖然早就被集成電路實(shí)施形式所取代，以用于實(shí)現(xiàn)復(fù)雜功能，但分立柵極仍可在僅需要非常簡單邏輯功能的情況下使用。

1. General description

The 74AUP2G06 provides two inverting buffers with open-drain output. The output of the device

is an open drain and can be connected to other open-drain outputs to implement active-LOW

wired-OR or active-HIGH wired-AND functions.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times

across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range

from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? High noise immunity

? Low static power consumption; ICC = 0.9 μA (maximum)

? Latch-up performance exceeds 100 mA per JESD 78B Class II

? Inputs accept voltages up to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8-B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A. Exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C