1. General description

The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is

determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A × C.

The output 2Y provides the Boolean function: 2Y = A × B + A × C.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times

across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range

from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing a damaging backflow current through the device when it is powered

down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? High noise immunity

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8-B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Low static power consumption; ICC = 0.9 μA (maximum)

? Latch-up performance exceeds 100 mA per JESD78 Class II

? Inputs accept voltages up to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial Power-down mode operation

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G885GS屬于集成電路（IC） > 門和反相器 - 多功能，可配置。安世半導體(中國)有限公司制造生產(chǎn)的74AUP1G885GS門和反相器 - 多功能，可配置可配置邏輯柵極系列產(chǎn)品能以與標準邏輯柵極類似的方式，對單個邏輯信號執(zhí)行基本邏輯運算，但并非局限于一個特定功能（例如 AND、NAND 等）。它們通常在內(nèi)部使用少量邏輯門來實現(xiàn)，經(jīng)過選擇和互連后，以便通過選擇操作數(shù)據(jù)所應(yīng)用的輸入以及任何未使用的輸入在驅(qū)動后的邏輯狀態(tài)，來配置所實現(xiàn)的整體邏輯功能。